CSTM6C00-MIDAS ¢º
Overview
MIDAS´Â 32-bit Embedded CPU¸¦ »ç¿ëÇÑ SOC(System On Chip)·Î¼ EFT/POS ½ÃÀåÀ»
°Ü³ÉÇÏ¿© ¼³°èµÇ¾ú´Ù. º¸´Ù ¹ü¿ëÀûÀ¸·Î ¸¸µé¾îÁø ´Ù¸¥ SOC¿Í´Â ´Þ¸® ½Ã½ºÅÛ ±¸¼º»ó ²À ÇÊ¿äÇÑ ±â´É¸¸À» ÁýÀûÇÏ¿© Àúºñ¿ëÀ¸·Î ±¸ÇöÇÒ ¼ö ÀÖ´Ù.
³»ÀåµÈ ¹ö½º ÄÁÆ®·Ñ·¯´Â ROM/SRAM/FLASH/SDRAMÀ» µ¿½Ã¿¡ Áö¿ø °¡´ÉÇϸç 8/16/32-bitÀÇ ¹ö½ºÆøÀ» Áö¿øÇÑ´Ù. µð½ºÇ÷¹À̸¦ À§ÇÑ
LCDÄÁÆ®·Ñ·¯´Â ³»ÀåÇÏÁö ¾ÊÀ½À¸·Î½á ¿ÜºÎ LCD¸ðµâÀÇ ÄÁÆ®·Ñ·¯¿Í Áߺ¹µÇÁö ¾Êµµ·Ï ÇÏ°í ¾Æ¿ï·¯ ¸ðµâ ÀÎÅÍÆäÀ̽º°¡ ¿ëÀÌÇϵµ·Ï ÇÏ¿´´Ù. ƯÈ÷
ISO7816-3(Identification Card) standardÀÇ Asynchronous T0, T1À» Áö¿øÇÒ ¼ö ÀÖ´Â ÄÁÆ®·Ñ·¯¸¦
³»ÀåÇÏ¿´´Ù. À̷νá Smart CardÀÇ ControlÀº SoftwareÀÇ °ü¿© ¾øÀÌ Hardware°¡ Card Insertion, Auto
Activation Sequence, De-Activation Sequence( Card Removal/ Finish ) , Data
Receive/Transmit¸¦ È¿°úÀûÀ¸·Î ProcessingÇÏ¿© Interrupt StatusÀ» ÆÄ¾ÇÇÏ¿© Interrupt Routine¿¡¼
¸ðµç 󸮰¡ ÀÌ·ç¾î Áöµµ·Ï DesignµÇ¾î ÀÖ´Ù.
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Features
¡ß 160 PQFP ¡ß 32-bit Embedded CPU
-
32-bit architecture -
Simple instruction
and high code density with 16 bit fixed length instruction -
Up to 60MHz
operation frequency - 32x32 = 32 hardware multiplier -
Support software
development environment - GNU C compiler and GNU debugger ¡ß Cache controller -
4KB cache size -
Two-way write back cache with write
buffer - LRU(Least Recently Used) algorithm ¡ß Bus controller -
Support 8/16/32 bit data bus
width - Support SDRAM, SRAM FLASH and ROM -
Programmable access cycle for
various memory type - 256MB address range consists of 8 banks - each bank has
32MB address range ¡ß Interrupt controller -
19 Interrupt source (Watch-dog
timer/3-Timer/2-UART/3-SIO/8-External interrupt/Keypad/I2C) -
Vectored
interrupt mode and pending ¡ß LCD
interface - Follow Intel microprocessor interface -
Dedicate
chip select pin(LCD_nCS) ¡ß Printer interface -
Follow UART interface ¡ß Keypad interface -
Support up to 8x8 key matrix -
Auto scan and
interrupt processing method ¡ß Serial interface -
2 UART full signal and 3 SIO ¡ß I2C -
I2C master function -
Support 100kHz Normal
mode and 400kHz fast mode ¡ß Timer - Watch-dog timer and 3 Timer ¡ß ISO7816-3 -
Data length : 8 bits -
Parity bit generation and
checking - Transmission of error signal (parity error) in receive mode -
Error
signal detection and automatic data retransmission in transmit mode -
Direct
convection and inverse convection both supported -
Built-in baud rate generator
allows any bit rate selected - Each channel have 8 interrupt source -
Half
duplex communication - 2 module are integrated - one is dedicated and another
is expandable
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Block Diagram
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Data sheet PDF Mannual
PDF
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